View DNC5X3125_1233575.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Overview
The DNC5X3125 is a low-cost, low-power transceiver macrocell. It is used for data transmission over fiber or coaxial media in conformance with IEEE* 802.3z Gigabit Ethernet specification and Fibre Channel ANSI X3T11 at 1.0 Gbits/s and 1.25 Gbits/s. The transmitter section accepts parallel 10-bit 8b/10b encoded data that is latched on the rising edge of TBC. It also accepts the low-speed, TTL compatible system clock, REFCLK, and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data is then available at the differential PECL outputs, terminated in 50 or 75 to drive either an optical transmitter or coaxial media. The receive section receives high-speed serial data at its differential PECL input port. This data is fed to the digital clock recovery section, which generates a recovered clock and retimes the data. The retimed data is deserialized and presented as 10-bit parallel data on the output port. A divided-down version of the recovered clock, synchronous with parallel data bytes, is also available as a TTL compatible output. The receive section recognizes the comma character and aligns the comma-containing byte on the word boundary, when ENCDET = 1.
Features
s
Designed to operate in Ethernet, fibre channel, FireWire or backplane applications. Operationally compliant to IEEE 802.3z Gigabit Ethernet specification. Operationally compliant to Fibre Channel ANSI X3T11. Provides FC-0 services at 1.0 Gbits/s-- 1.25 Gbits/s (10-bit encoded data rate). 100 MHz--125 MHz differential or single-ended reference clock. 10-bit parallel interface. 8b/10b encoded data. High-speed comma character recognition (K28.1, K28.5, K28.7) for latency-sensitive applications and alignment to word boundary. Two 50.0 MHz--62.5 MHz receive-byte clocks. Single analog PLL design requires no external components for the frequency synthesizer. Novel digital data lock in receiver avoids the need for multiple analog PLLs. Expandable beyond single-channel SERDES. PECL high-speed interface I/O for use with optical transceiver or coaxial copper media. Requires one external resistor for PECL output reference level definition. Low-power digital 0.25 m CMOS technology. 3.3 V 5% power supply. 0 C--70 C ambient temperature.
s
s
s
s s s
s s
s
s s
s
s s s
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. ANSI is a registered trademark of American National Standards Institute. FireWire is a registered trademark of Apple Computer, Inc.
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Table of Contents
Contents Page Table Page
Overview .....................................................................1 Features.......................................................................1 Functional Description ................................................3 Transmitter Section.................................................. 3 Receiver Section..................................................... 3 Lock to Reference ....................................................3 Byte Alignment .........................................................4 Parallel Output Port ................................................. 4 Loopback Mode Operation ......................................4 Powerup Sequence .................................................5 Macrocell Reset .......................................................5 Sleep Mode ..............................................................5 Block Diagrams ........................................................6 Input/Output Information .............................................8 Electrical Specifications ..............................................9 Transmitter ...............................................................9 Receiver .................................................................10 Timing Characteristics ..............................................11 Serial Timing ..........................................................11 Receiver Section Timing ........................................12 Receiver Port Timing ..............................................12 Transmitter Section Timing.................................... 13 Application Information ............................................. 14 Test Modes ...............................................................16
Table 1. Receive Circuit Operating Modes .................. 3 Table 2. Definition of Bit Transmission/ Reception Order ............................................ 4 Table 3a. I/O Channel Interface .................................. 8 Table 3b. I/O Control/PLL Interface Connections ....... 8 Table 3c. Power Connections ..................................... 9 Table 4. Reference Clock Specifications (REFCLK and REFCLKN) ............................................. 9 Table 5. PLL Specifications ........................................ 9 Table 6. Output Jitter at 1.0 Gbits/s--1.25 Gbits/s ..... 9 Table 7. Receive Input Data Rate ............................. 10 Table 8. Data Lock Characteristics ........................... 10 Table 9. Power Dissipation ....................................... 10 Table 10. dc Electrical Specifications ....................... 10 Table 11. Absolute Maximum Ratings ...................... 10 Table 12. Serial Output Timing Levels ...................... 11 Table 13. Serial Input Interface Timing ..................... 11 Table 14. Receiver Parallel Port Timing ................... 12 Table 15. Transmitter Timing at Parallel Interface ..... 13 Table 16. External Resistor Value vs. Differential Output Level Viewing ................................ 15 Table 17. Test Modes ............................................... 16
Figure
Page
Figure 1. Quad Gigabit Ethernet Transceiver Block Diagram.............................................. 6 Figure 2. DNC5X3125 Single-Channel Transceiver Functional Block Diagram ........................... 7 Figure 3. Serial Interface Timing ............................... 11 Figure 4. Receiver Section Timing ............................ 12 Figure 5. Receiver Port Timing ................................ 12 Figure 6. Parallel Interface Transmit Timing ............. 13 Figure 7. Reference Clock Connections with Single-Ended Source ................................. 14 Figure 8. Typical Termination for a Single-Channel, High-Speed, Serial Transmit and Receive Port in a 50 Backplane Application ........ 14 Figure 9. Typical Termination for a Single-Channel, High-Speed Serial Transmit/Receive Port Interfacing a 5 V GBIC Transceiver............ 15
2
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Receiver Section
The receiver circuit extracts clock from and retimes the serial input data. The data are input to the receiver on differential PECL buffers. External termination resistors are supplied by the user in accordance with ANSI standard, X3T11. The serial differential inputs, HDINP and HDINN, are ac-coupled to the device and internally biased to the PECL input common-mode range center. The receiver data-retiming circuit uses a digital timing recovery loop that compares the phase of the input data to multiple phases of the on-device VCO in the transmit section. One of the phases is chosen to retime the receive data. A digital low-pass filter is used in the timing recovery loop to reject jitter from the data input. A novel phase interpolation circuit permits the retiming clock's phase to be stepped with fine resolution for precise alignment of the sampling clock within the data eye. Use of this digital data-locking scheme for each receiver advantageously avoids the use of multiple analog phase-lock loops on-device that can potentially injection lock to one another. Additionally, the digital data-locking loop maintains precise loop dynamics, hence the jitter transfer function is process and temperature independent.
Functional Description
The DNC5X3125 transceiver provides for data transmission over fiber or coaxial media at 1.0 Gbits/s to 1.25 Gbits/s. The block diagram of the macrocell used as a quad-channel transceiver is shown in Figure 1 and the single-channel macrocell design is shown in Figure 2. The input/output designations are given in Table 3.
Transmitter Section
The typical transmit and receive, high-speed I/O interfacing for single-channel applications is shown in Figures 8 and 9. The transmitter brings in 8b/10b encoded bits in 10-bit parallel form for up to 1.25 Gbits/s transmission and converts the data to serial format. The serial nonreturn to zero (NRZ) bits are then shifted out of the device at a maximum rate of 1.25 Gbits/s. Internally, the device uses two parallel shift registers that operate at half rate (i.e., a maximum of 625 MHz) for reduced power consumption. The two shift registers drive the PECL output buffer in an interleaved manner to construct the 1.25 Gbit/s output data stream. The transmit shift register and other circuits are driven with clocks generated from a 625 MHz internal clock. This internal clock is sourced from a voltage controlled oscillator (VCO) that is locked to the external reference of 100 MHz--125 MHz. The internal transmit phaselock loop multiplies the frequency of the input reference clock by a factor of 5, and controls the transmit jitter bandwidth with appropriate design of the jitter transfer function. The transmit phase-lock loop generates multiple clock phases that are all used by each of the four receiver circuits. The clock phases are derived from the transmit VCO.
Lock to Reference
The receive circuit has two modes of operation, lock to reference, and lock to data with retiming. When no data or invalid data is present on the HDINP and HDINN input nodes, the user can program the device to ignore the input data by setting LCKREFN equal to logic 0. In this mode, neither the PECL input buffer nor the RX parallel data bus toggles. In normal operations, LCKREFN is a logic 1 and the receiver attempts to lock to the incoming data. If the input data is invalid or outside the nominal frequency range, the receive digital PLL will simply ramp the phase of the output clock until it locks to data.
Table 1. Receiver Circuit Operating Modes* Mode Lock to Reference Lock to Receive Data Continually attempts to lock to data. Not applicable.
LCKREFN = 1 (normal operation) Not applicable LCKREFN = 0 Lock to clock, output data does not toggle. Disable PECL input buffer.
* REFCLK requirements are given in Table 4.
Lucent Technologies Inc.
3
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Parallel Output Port
Timing for the parallel output data and the 50 MHz to 62.5 MHz receive-byte clock is given in Table 14. Two low data-rate, receive-byte clocks are available as outputs during use of the parallel output port in 10-bit mode. RXCLK1 is the receive-byte clock used by the protocol device to register bytes 0 and 2. RXCLK0 is the receive-byte clock used by the protocol device to register bytes 1 and 3, and it is 180 degrees out of phase with RXCLK1. Both RXCLK1 and RXCLK0 can be stretched during byte alignment but not truncated or slivered. The maximum allowable frequency of these two clocks under all circumstances, excluding start-up, will not exceed 80 MHz. The start-up time is specified as 1 ms.
Functional Description (continued)
Byte Alignment
When ENCDET = 1, the DNC5X3125 recognizes the comma character and aligns this 10-bit character to the word boundary, bits RX[0:9]. COMDET = 1 when the parallel output word contains a byte-aligned comma character. The COMDET flag will continue to pulse a logic 1 whenever a byte aligned comma character is at the parallel output port, independent of ENCDET. When ENCDET = 0, there are two possible scenarios depending upon when the comma character is received: 1. If byte-alignment had been previously achieved when ENCDET had been a logic 1, the COMDET flag will continue to pulse a logic 1 whenever a bytealigned comma character is at the parallel output port. If a comma character occurs that is not on the word boundary, no attempt will be made to align this comma character, and the COMDET flag will remain at a logic 0. 2. If byte-alignment had not been previously achieved when ENCDET had been a logic 1, then the first (and only the first) comma character received will be aligned to the word boundary. COMDET will pulse when the comma character is aligned to the word boundary.
Loopback Mode Operation
A control signal input, EWRAP selects between two , possible sets of inputs: normal data (HDINP, HDINN) or internal loopback data. When EWRAP = 1, the serial output ports, HDOUTP and HDOUTN, remain active. The serial transmit data prior to the PECL output driver is directed to the data recovery circuit, where the clock is recovered and data is resynchronized to the recovered clock. Retimed data and clock then go to the serial-to-parallel converter.
Table 2. Definition of Bit Transmission/Reception Order Serial Transmit/Receive Rate 1.0 Gbits/s to 1.25 Gbits/s TX[9:0] TX[0] bit serially transmitted first at HDOUTP HDOUTN , RX[9:0] RX[0] bit received first at serial inputs, HDINP HDINN ,
4
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Functional Description (continued)
Powerup Sequence
An appropriate powerup reset (PUR) standard cell must be placed in the ASIC to hold the transceiver in reset until full power is supplied to the macrocell. REFCLK must be active at the time the PUR output goes low and must stay active while powered up, unless in Reset. When PUR and signals RESET, BYPPLL, and LPWR are all low, the following start-up sequence occurs: 1. 0 s--32 s, the analog PLL is held at minimum frequency to allow dc bias to settle. 2. 32 s--262 s, the analog PLL has locked in and receiver analog circuits start to lock in. 3. 262 s--326 s, the receiver analog circuits are locked; receiver starts to lock onto incoming data. 4. After 358 s, receiver is locked onto incoming data and can be viewed at the parallel output ports. The comma detect circuit is enabled at this point allowing byte alignment if ENCDET = 1. If LCKREFN goes low after the 358 s, the receiver will sit idle. When LCKREFN goes high, the receiver will be locked onto data after 2 s.
Macrocell Reset
The RESET input to the macrocell is an active-high. When activated with a pulse duration of 1 s, the RESET signal globally resets the macrocell and the following is performed: 1. The single analog PLL is forced to operate at the minimum frequency possible for its VCO. The PLL will not be locked in this condition. 2. The high-speed serial output HDOUTP is forced to a PECL logic 0, HDOUTN to logic 1. 3. The deserializer clocks are reset, input data at HDINP HDINN is ignored and the RX[9:0] signals remain in their , previous state. 4. The phase interpolation/selection circuits are deactivated and the selected phase is reset. 5. The receiver digital low-pass filter in the DPLL is reset. Normally, a reset is not necessary for correct operation, although a reset can aid rapid lock-in of the internal PLL circuitry.
Sleep Mode
The DNC5X3125 has a sleep mode that is activated by enabling LPWR. In this mode, a divided-down version of the REFCLK is used to refresh the dynamic circuits within the transceiver. The PLL is powered down in this mode also. LCKREFN can also be activated to reduce the power even further. Note that complete power down for IDDQ testing is not supported due to the dynamic logic used in the high-speed sections of the transceiver. The lock-in sequence timing is needed when coming out of sleep mode.
Lucent Technologies Inc.
5
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Functional Description (continued)
Block Diagrams
LCKREFN[A:D]
COMDET[A:D]
ENCDET[A:D]
LPWR
RESET
EWRAP[A:D]
TBC[A:D]
OLREF OLRVS
HDINAP HDINAN HDOUTAP HDOUTAN HDINBP HDINBN HDOUTBP HDOUTBN
2 2 TRANSCEIVER A
RXA[9:0] TXA[9:0]
2 2 TRANSCEIVER B
RXB[9:0] TXB[9:0] TEST[5:1] LDST[A:D] BYPPLL RXCLK0[A:D] RXCLK1[A:D]
TEST CIRCUITS REFCLK REFCLKN 2 ANALOG PLL
HDINCP HDINCN HDOUTCP HDOUTCN HDINDP HDINDN HDOUTDP HDOUTDN
2 2 TRANSCEIVER C
RXC[9:0] TXC[9:0]
2 2 TRANSCEIVER D
RXD[9:0] TXD[9:0]
5-8808(F)
Figure 1. Quad Gigabit Ethernet Transceiver Block Diagram
6
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Functional Description (continued)
Block Diagrams (continued)
OLREF* OLRVS*
TX[9:0]
DATA IN SERIALIZER SERIAL DATA OUT PECL
HDOUTP*
TBC
LOAD
HDOUTN*
TEST[5:1] / LDST BYPPLL REFCLK* REFCLKN* ANALOG PLL RESET GLOBAL CONTROL LPWR PUR EWRAP ENPLLO PLLFB
DESERIALIZER PHASE SELECT/ INTERPOLATION
HDINP* DIGITAL LOW-PASS FILTER PHASE DETECTOR PECL HDINN*
RX[9:0] RXCLK0 RXCLK1 COMDET DATA-RETIMING, SERIAL-TO-PARALLEL CONVERSION AND COMMA DETECTION SERIAL DATA IN
5-8809(F)
* These signals brought to I/O pads for SERDES integration. Synchronous with REFCLKN.
Figure 2. DNC5X3125 Single-Channel Transceiver Functional Block Diagram
Lucent Technologies Inc.
7
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Input/Output Information
Table 3a. I/O Channel Interface Name TX[9:0] I/O Input Level CMOS Description Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/ 10b encoded data byte, clocked-in on the rising edge of TBC. TX0 is the least significant bit. Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data type, clocked-out on the alternate rising edges of RXCLK0, RXCLK1. RX0 is the least significant bit. Transmit Byte Clock (100 MHz--125 MHz). Synchronous with REFCLKN. Receive Byte Clock 0. Receive Byte Clock 1. Enable Comma Detection. Byte-Aligned Comma Detect. Loopback at Serial I/O. Lock Receiver to Clock. Differential Serial Inputs. Differential Serial Outputs. Load TEST[5:1] Inputs.
RX[9:0]
Output
CMOS
TBC RXCLK0 RXCLK1 ENCDET COMDET EWRAP LCKREFN HDINP HDINN , HDOUTP HDOUTN , LDST
Input Output Output Input Output Input Input Input Output Input
TTL/CMOS CMOS CMOS CMOS CMOS CMOS CMOS PECL PECL CMOS
Table 3b. I/O Control/PLL Interface Connections Name OLREF OLRVS LPWR RESET TEST5 TEST4 TEST3 TEST2 TEST1 BYPPLL REFCLK, REFCLKN PUR PLLFB ENPLLO I/O Input/Output Input/Output Input Input Input Input Input Input Input Input Input Input Output Output Level Analog Analog CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS PECL or TTL/ CMOS CMOS CMOS CMOS Description PECL Level Set Resistor Terminal 1. PECL Level Set Resistor Terminal 2. Macrocell Low-Power Mode. Macrocell Reset (Active-High). Global Test Control Input. Local Test Control Input. Local Test Control Input. Local Test Control Input. Local Test Control Input. Test Control--PLL Bypass Mode. Reference Clock Input (100 MHz--125 MHz). Powerup Reset. PLL Feedback Clock. Enable PLL Feedback.
8
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Input/Output Information (continued)
Table 3c. Power Connections Name VDDG VDDR VDDT VDDP VDD VSSG VSSR VSST VSSP VSS Description Global Digital Power. High-Speed Receive Power. High-Speed Transmit Power. PLL Power. Power. Global Digital Ground. High-Speed Receive Ground. High-Speed Transmit Ground PLL Ground. Ground.
Electrical Specifications
Transmitter
Table 4. Reference Clock Specifications (REFCLK and REFCLKN) Parameter Frequency Range Frequency Tolerance Duty Cycle* Rise Time (PECL) Fall Time (PECL) Rise Time (TTL/CMOS) Fall Time (TTL/CMOS) In-band Jitter 1 Gbits/s--1.25 Gbits/s Out-of-Band Jitter
* Measured at 50% amplitude point.
Minimum 100 -100 40 -- -- -- -- -- --
Maximum 125 100 60 0.8 0.8 1.5 1.5 30 50
Unit MHz ppm % ns ns ns ns ps p-p ps p-p
Table 5. PLL Specifications Parameter Bandwidth Jitter Peaking Lock Time Minimum -- -- -- Typical 1.5 0.5 -- Maximum -- -- 230 Unit MHz dB s
Table 6. Output Jitter at 1.0 Gbits/s--1.25 Gbits/s Parameter Deterministic Random Total Minimum -- -- -- Maximum 0.08 0.12 0.2 Unit UI p-p UI p-p UI p-p
Lucent Technologies Inc.
9
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Electrical Specifications (continued)
Receiver
Table 7. Receiver Input Data Rate Parameter Data Rate Frequency Tolerance with REFCLK Table 8. Data Lock Characteristics Parameter Bandwidth Jitter Peaking Lock time*
* Data pattern: 111110000 . . . Data pattern: 101010 . . .
Minimum 1.0 -100
Maximum 1.25 100
Unit Gbits/s ppm
Minimum 0.3 * -- --
Typical -- 0.5 --
Maximum 1
Unit MHz dB s
-- 2
Table 9. Power Dissipation* Parameter Power Sleep Mode
* Depending on application (PCB layout, etc.)
Minimum -- --
Maximum 750 TBD
Unit mW mW
Table 10. dc Electrical Specifications Parameter Supply Voltage Diff. PECL Output Diff. PECL Input Symbol VDD,VDDA -- -- Condition -- Load, as in Figure 8 Source configuration, as in Figure 8 Minimum 3.135 800 400 Typical 3.3 -- -- Maximum 3.465 -- 1600 Unit V mV mV
Table 11. Absolute Maximum Ratings Parameter Supply Voltage TTL High Input Voltage PECL Output Current Junction Operating Temperature Storage Temperature Minimum 3.135 3.0 -- 0 -65 Maximum 3.465 3.6 16 125 150 Unit V V mA C C
10
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Timing Characteristics
Serial Timing
Table 12. Serial Output Timing Levels Description Rise Time 20%--80% Fall Time 80%--20% Common Mode Differential Swing Load (See Table 16.) Minimum 0.17 0.17 VDD/2 - 0.1 0.8 50 Typical 0.2 0.2 VDD/2 -- -- Maximum 0.22 0.22 VDD/2 + 0.1 1.6 75 Unit ns ns V V p-p
DWIN VDIFF
tF/tR
Figure 3. Serial Interface Timing Table 13. Serial Input Interface Timing Description Rise Time (tR) Fall Time (tF) Differential Swing (VDIFF) Source Impedance Data Eye Opening (DWIN) Minimum 150 150 0.4 50 320 Maximum 225 225 1.6 75 -- Unit ps ps V p-p ps
5-8812(F)
.
Lucent Technologies Inc.
11
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Timing Characteristics (continued)
Receiver Section Timing
HDNIP K28.5 RECOVERED CLOCK (INTERNAL) D7.2 D0.0 D1.0
RXCLK1
RXCLK0
RX[9:0]
K28.5
D7.2
COMDET
5-8813(F)
Figure 4. Receiver Section Timing
Receiver Port Timing
RXCLK PERIOD RXCLK1 LOW RXCLK1 RXCLK1 HIGH
RXCLK0 tSKEW
RX tS
RX0 tH
RX1
RX2 tS
RX3 tH
5-8814(F)
Figure 5. Receiver Port Timing Table 14. Receiver Parallel Port Timing
Symbol Parameter RXCLK[1:0] Frequency* RXCLK[1:0] Low RXCLK[1:0] High RXCLK[1:0] (0.4 V to 2.6 V) Data Output (0.4 V to 2.6 V) Setup Time Hold Time Skew Min -- 7.0 7.0 0.2 0.2 3.0 2.0 -- Max 62.5 9.0 9.0 0.5 0.5 -- -- 1.0 Unit MHz ns ns ns ns ns ns ns
-- -- --
tR/F tR/F tS tH tSKEW
* 1.25 Gbits/s. 0.5 pF load.
12
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Timing Characteristics (continued)
Transmitter Section Timing
TBC*
TX[9:0]
155 155
126 126
375 375
34A
SERIALIZED DATA
SYNTHESIZED CLOCK
5-8815(F)
* Synchronous with REFCLKN.
Figure 6. Parallel Interface Transmit Timing
Table 15. Transmitter Timing at Parallel Interface Description Data Setup Data Hold Rise Time Fall Time Minimum 2 2 -- -- Maximum -- -- 1 1 Unit ns ns ns ns Conditions With Positive Edge TBC With Positive Edge TBC -- --
Lucent Technologies Inc.
13
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Application Information
BIAS REFCLK CLOCK SOURCE REFCLKN INTERNAL CLOCK
BIAS DNC5X3125
5-8010(F)(F
Figure 7. Reference Clock Connections with Single-Ended Source
10 HDOUTP
ZO = 50
0.01 F HDINP
50 RX[9:0] TXA[9:0] TRANSMIT DNC5X3125 50 TBC HDOUTN 10 0.01 F ZO = 50 HDINN 100 0.1 F RXCLK1 RXCLK0 RECEIVE DNC5X3125
OLREF
OLRVS
* * External resistor connected between OLREF and OLRVS. See Table 16 for external resistor value required for differential output swing. Damping resistor, maximum = 10 .
Figure 8. Typical Termination for a Single-Channel, High-Speed Serial Transmit-and-Receive Port in a 50 Backplane Application
5-8811(F).c
14
Lucent Technologies Inc.
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Application Information (continued)
5V
68 10 HDOUTP ZO = 50 0.01 F TX (+)
50
191
TXA[9:0]
TRANSMIT LU5X31FT 0.1 F 50 191 ZO = 50 HDOUTN 10 0.01 F 68 OLREF OLVRVS 5V
TRANSMIT GBIC
TBC
TX (-)
*
5-8811(F)b
* External resistor connected between OLREF and OLRVS. See Table 16 for resistor value vs. termination impedance and output swing. Damping resistor, maximum = 10 .
Figure 9. Typical Termination for a Single-Channel, High-Speed Serial Transmit Port Interfacing a 5 V GBIC Transceiver Table 16. External Resistor Value vs. Differential Output Level Viewing Resistor Value () 7.5 K/11.25 K 5 K/7.5 K 4 K/6 K Termination Impedance () 50/75 Differential Output Voltage (V) 0.8 1.2 1.6
Lucent Technologies Inc.
15
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
Test Modes
Note: Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be modified or eliminated without prior notice. The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular channel. For example, if LDST = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDST = 0, the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B, C, D) via level sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test node used for both injection of signals as well as for monitoring points within the device. Table 17. Test Modes Global BYPPLL 0 0 0 Test1 1 1 1 Local Test Configuration Test2 1 1 1 Test3 1 1 0 Test4 1 0 1 Global Test5 X Output X Operation Normal operation. Analog PLL feedback signal viewed at TEST5. Transceiver operates normally except RX[9:0] output is from digital filter, not the serial data. Transceiver operates normally except RX[9:0] output is from digital filter and the analog PLL feedback signal is viewed at TEST5. Digital filter forced to count. Pulses applied at TEST4 increments accumulator, pulses at TEST5 decrements accumulator. RX[9:0] output is from digital filter, not the serial data. Digital filter forced to count. Pulses applied at TEST4 increments accumulator, pulses at TEST5 decrements accumulator. Parallel loopback. TX[9:0] = RX[9:0]. RX[9:0] remains active. Parallel loopback. TX[9:0] = RX[9:0] and analog PLL feedback signal viewed at TEST5. RX[9:0] remains active. RX[9:0] output is from digital filter, not the serial data. Receive channel is held in reset. BYPPLL overrides this reset. RX[9:0] output is from digital filter, not the serial data. Receive channel is held in reset. BYPPLL overrides this reset. Analog PLL feedback signal viewed at TEST5. Transmitter is held in reset. BYPPLL overrides this reset. Lucent Technologies Inc.
0
1
1
0
0
Output
0
1
0
1
P
P
0
1
0
0
P
P
0 0
0 0
1 1
1 1
1 0
X Output
0
0
1
0
1
X
0
0
1
0
0
Output
0
0
0
1
1
X
16
Advance Data Sheet March 2000
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Test Modes (continued)
Table 17. Test Modes (continued) Global BYPPLL 0 Test1 0 Local Test Configuration Test2 0 Test3 1 Test4 0 Global Test5 Output Operation Transmitter is held in reset. BYPPLL overrides this reset. Analog PLL feedback signal viewed at TEST5. Transmitter and receiver are held in reset. RX[9:0] output is from digital filter, not the serial data. Transmitter and receiver are held in reset. RX[9:0] output is from digital filter, not the serial data. Analog PLL feedback signal viewed at TEST5. Analog PLL is bypassed for low speed functional test. A low speed clock is input to TEST4, and a quadrature clock is applied to TEST5. Frequency of clocks is 5 x REFCLK, but here REFCLK is lowered to about 1 MHz. Analog PLL is bypassed for low speed functional test. A low speed clock is input to TEST4, and a quadrature clock is applied to TEST5. Frequency of clocks is 5 x REFCLK, but here REFCLK is lowered to about 1 MHz. RX[9:0] output is from digital filter, not the serial data.
0
0
0
0
1
X
0
0
0
0
0
Output
1
X
X
1
C-0
C-90
1
X
X
0
C-0
C-90
Lucent Technologies Inc.
17
DNC5X3125 Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet March 2000
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
March 2000 DS99-398LAN

▲Up To Search▲

Price & Availability of DNC5X3125

	To Download DNC5X3125 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .